As transistor sizes continue to decrease, thermal engineers are investigating ways to decouple the electron and phonon transport physics that are typically combined in the classical Fourier’s Law of Conduction. At the various semiconductor/metallic interfaces, heat traveling in the phonons in the semiconductor material must first conduct heat to the phonons in the metal. The phonons in the metal must then transfer heat to the electrons in the metal. These extra transport steps add additional resistances that are not present if only contact resistance and Fourier type conduction are included. MD, ab initio and other advanced modeling techniques can be used to estimate the atomic structure at the interface and the “bottlenecks” that occur when conducting between phonons and electrons at the interface between two materials.
Electronics cooling is currently one of the largest areas for thermal research and development. The decreasing size and increasing power consumption in transistors have led to many thermal challenges. MD, ab initio and BTE modeling techniques are required to accurately predict the chip level thermal transport process. Accurate modeling of the electron conduction, phonon conduction, and energy transfer between electrons and phonons is required to capture the heating process in a transistor. This technical understanding is important since the relative proportions of electron conduction, phonon conduction and electron to phonon conversion are important.
ACT has developed several in-house models and simulation codes to successfully simulate multiphysics behavior in semiconductor materials made of SiC and GaN. These tools enable simulation of coupled field problems and provide previously unavailable insights to materials and thermal engineers involved in semiconductor chip design.
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